This invention relates generally to digital communications systems and more specifically to communication systems for interconnecting the processors of parallel computing systems.
The processing demands of modern information systems require very high information throughput, which may exceed the capabilities of serial data processors. Computers using parallel or simultaneous processors are used to maximize throughput. In general, such computing systems utilize large numbers of similar processors which are interconnected in a fixed manner to adapt them for optimum performance on a specific computational task. Such a fixed interconnection, however, may not be optimal for other tasks. For example, a fixed tree interconnection such as that illustrated in FIG. 1 may be optimal for a certain processing tasks such as searching, but may not be so well adapted for matrix operations. Various topologies are described in the article "A Study of Interconnection Networks" by Feng, published at pp. 12-27 of the Dec., 1981 issue of IEEE Computer.
Switched interconnection networks are known which allow adaptation of the interconnections between processors to various tasks. The physical implementations of such schemes tend to be complex and costly to manufacture. Manufacturing is well adapted for economical fabrication of large numbers of identical modules. When customized or low quantity modules must be made, or customized interconnections from module to module must be provided, the cost of manufacture increases dramatically.
A modular processor interconnection scheme is desired which is readily adaptable to a large number of different types of processor interconnections, and in which the number of connections made within each module is relatively large by comparison with the number of off-module connections to thereby reduce manufacturing costs.